The complementary metal oxide semiconductor (CMOS) and bipolar-complementary metal oxide semiconductor (BiCMOS) technologies offer low power dissipation, good noise performance, high packing density, et cetera in analog and digital circuit design. They have contributed significantly to the advancement of wireless communication and sensing systems and are presently inevitable devices in these systems. As the technologies and device performance have advanced into the millimeter-wave regime over last two decades, accurate S-parameters of CMOS and BiCMOS devices at millimeter-wave frequencies are highly demanded for millimeter-wave radio-frequency integrated-circuit (RFIC) design. The accuracy of these S-parameters is absolutely essential for extracting accurately the device parameters and small- and large-signal models. The conventional extraction techniques using both impedance standard substrate and de-embedding technique have been replaced by on-wafer calibration techniques implementing calibration standards fabricated on the same wafer together with the device under test (DUT) in virtue of accurate characterization over wide frequency and at high frequencies. However, some challenges for the on-wafer calibration still remain where the calibration is conducted over a wide frequency range covering millimeter-wave frequencies with a DUT such as bipolar junction transistor (BJT). The ends of the interconnects for the open and load standards are inherently very close to each other since it depends on the spacing between base (or collector) and emitter of the BJT (about 0.25 μm), hence not only causing significant gap and open-end fringing capacitances, which leads to substantial undesired effects for device characterization at millimeter-wave frequencies, but also making it impossible to place resistors within such narrow gaps for the load standard design. In order to resolve the structural issue of the conventional on-wafer calibration standards, a new method implementing both on-wafer calibration and electromagnetic (EM)-based de-embedding has been developed. In the newly developed technique, appropriate spacing in the on-wafer calibration standards, which minimizes the parasitic capacitance between the close open-ends and sets enough space to place the load standard's resistors, is determined based on EM simulations, and the non-calibrated part within the spacing consisting of interconnects and vias is extracted by the EM-based de-embedding. The developed procedure with the on-wafer calibration and the EM-based de-embedding characterizes the S-parameters of BJTs in 0.18-µm SiGe BiCMOS technology from DC to 67 GHz. The measured results show sizable differences in insertion loss and phase between the on-wafer characterizations with and without the EM-based de-embedding, demonstrating that the developed on-wafer characterization with EM-based de-embedding is needed for accurate characterization of devices at millimeter-wave frequencies, which is essential for the design of millimeter-wave wireless communication and sensing systems.


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